JTAG J-Link learning notes

11.1 JTAG

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11.1.1 Test access port (TAP)

JTAG defines a TAP (Test access port). The TAP is a general-purpose port that can
provide access to many test support functions built into a component. It is composed
as a minimum of the three input connections (TDI, TCK, TMS) and one output connection
(TDO). An optional fourth input connection (nTRST) provides for asynchronous
initialization of the test logic.

11.1.2 Data registers

JTAG requires at least two data registers to be present: the bypass and the boundary-
scan register. Other registers are allowed but are not obligatory.

Bypass data register

A single-bit register that passes information from TDI to TDO.

Boundary-scan data register

A test data register which allows the testing of board interconnections, access to
input and output of components when testing their system logic and so on.

11.1.3 Instruction register

The instruction register holds the current instruction and its content is used by the
TAP controller to decide which test to perform or which data register to access. It
consist of at least two shift-register cells.

PIN Type Explanation

TCK Input The test clock input (TCK) provides the clock for the test
logic.

TDI Input Serial test instructions and data are received by the test
logic at test data input (TDI).

TMS Input The signal received at test mode select (TMS) is
decoded by the TAP controller to control test operations.

TDO Output Test data output (TDO) is the serial output for test
instructions and data from the test logic.

nTRST Input
(optional)

The optional test reset (nTRST) input provides for asynchronous initialization of the TAP controller.

Table 11.1: Test access port

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11.1.4 The TAP controller

The TAP controller is a synchronous finite state machine that responds to changes at
the TMS and TCK signals of the TAP and controls the sequence of operations of the
circuitry.

TAP controller state diagram

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11.1.4.1 State descriptions

Reset

The test logic is disabled so that normal operation of the chip logic can continue
unhindered. No matter in which state the TAP controller currently is, it can change
into Reset state if TMS is high for at least 5 clock cycles. As long as TMS is high, the
TAP controller remains in Reset state.

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11.2 Embedded Trace Macrocell (ETM)

Embedded Trace Macrocell (ETM) provides comprehensive debug and trace facilities
for ARM processors. ETM allows to capture information on the processor’s state without
affecting the processor’s performance. The trace information is exported immediately
after it has been captured, through a special trace port.

Microcontrollers that include an ETM allow detailed program execution to be recorded
and saved in real time. This information can be used to analyze program flow and
execution time, perform profiling and locate software bugs that are otherwise very
hard to locate. A typical situation in which code trace is extremely valuable, is to find
out how and why a "program crash" occurred in case of a runaway program count.
A debugger provides the user interface to J-Trace and the stored trace data. The
debugger enables all the ETM facilities and displays the trace information that has
been captured. J-Trace is seamlessly integrated into the IAR Embedded Workbench®
IDE. The advanced trace debugging features can be used with the IAR C-SPY debugger.

11.2.1 Trigger condition

The ETM can be configured in software to store trace information only after a specific
sequence of conditions. When the trigger condition occurs the trace capture stops
after a programmable period.

11.2.2 Code tracing and data tracing

Code trace

Code tracing means that the processor outputs trace data which contain information
about the instructions that have been executed at last.

Data trace

Data tracing means that the processor outputs trace data about memory accesses
(read / write access to which address and which data has been read / stored). In
general, J-Trace supports data tracing, but it depends on the debugger if this option
is available or not. Note that when using data trace, the amount of trace data to be
captured rises enormously.

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