Sunday, 7 July 2013

CMSIS-CORE study notes
























CMSIS-CORE Overview

file:///L:/FongMpu/cmsis/CMSIS/Documentation/Core/html/index.html

CMSIS-CORE implements the basic run-time system for a Cortex-M device and gives the user access to the processor core and the device peripherals. In detail it defines:

Hardware Abstraction Layer (HAL) for Cortex-M processor registers with standardized definitions for the SysTick, NVIC, System Control Block registers, MPU registers, FPU registers, and core access functions.

System exception names to interface to system exceptions without having compatibility issues.

Methods to organize header files that makes it easy to learn new Cortex-M microcontroller products and improve software portability. This includes naming conventions for device-specific interrupts.

Methods for system initialization to be used by each MCU vendor. For example, the standardized SystemInit() function is essential for configuring the clock system of the device.

Intrinsic functions used to generate CPU instructions that are not supported by standard C functions.

A variable to determine the system clock frequency which simplifies the setup the SysTick timer.

This chapter provides details about the CMSIS-CORE and contains the following sections:

Using CMSIS in Embedded Applications describes the project setup and shows a simple program example.

Template Files describes the files of the CMSIS-CORE in detail and explains how to adapt template files provided by ARM to silicon vendor devices.

MISRA-C:2004 Compliance Exceptions describes the violations to the MISRA standard.

Reference describe the features and functions of the Device Header File <device.h> in detail.

Data Structures describe the data structures of the Device Header File <device.h> in detail.



Using CMSIS in Embedded Applications

To use the CMSIS-CORE the following files are added to the embedded application:

Startup File startup_<device>.s with reset handler and exception vectors.

System Configuration Files system_<device>.c and system_<device>.h with general device configuration (i.e. for clock and BUS setup).

Device Header File <device.h> gives access to processor core and all peripherals.

Note

The files Startup File startup_<device>.s and System Configuration Files system_<device>.c and system_<device>.h may require application specific adaptations and therefore should be copied into the application project folder prior configuration. The Device Header File <device.h> is included in all source files that need device access and can be stored on a central include folder that is generic for all projects.

The Startup File startup_<device>.s is executed after reset and calls SystemInit. After the system initialization control is transferred to the C/C++ run-time library which performs initialization and calls the main function in the user code. In addition the Startup File startup_<device>.s contains all exception and interrupt vectors and implements a default function for every interrupt. It may also contain stack and heap configurations for the user application.

The System Configuration Files system_<device>.c and system_<device>.h performs the setup for the processor clock. The variable SystemCoreClock indicates the CPU clock speed. System and Clock Configuration describes the minimum feature set. In addition the file may contain functions for the memory BUS setup and clock re-configuration.

The Device Header File <device.h> is the central include file that the application programmer is using in the C source code. It provides the following features:

Peripheral Access provides a standardized register layout for all peripherals. Optionally functions for device-specific peripherals may be available.

Interrupts and Exceptions (NVIC) can be accessed with standardized symbols and functions for the Nested Interrupt Vector Controller (NVIC) are provided.

Intrinsic Functions for CPU Instructions allow to access special instructions, for example for activating sleep mode or the NOP instruction.

Intrinsic Functions for SIMD Instructions [only Cortex-M4] provide access to the DSP-oriented instructions.

Systick Timer (SYSTICK) function to configure and start a periodic timer interrupt.

Debug Access are functions that allow printf-style I/O via the CoreSight Debug Unit and ITM communication.

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CMSIS study notes




























CMSIS study notes

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uv4 cm0 hello example study notes





































uv4 cm0 hello example.

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LPC1115 LPCXPRESSO BOARD - embeddedartists

LPC1115 LPCXPRESSO BOARD - embeddedartists

http://www.embeddedartists.com/products/lpcxpresso/lpc1115_xpr.php

The LPC1115 LPCXpresso board with NXP's ARM Cortex-M0 microcontroller has been designed to make it as easy as possible to get started with Cortex-M0. The LPCXpresso comprises a target board combined with a JTAG debugger. A free Eclipse-based IDE from NXP/Code Red is also included.

The LPC1115 has 8 kB SRAM, 64 kB Flash, SSP, I2C, UART, ADC, etc. Embedded Artists also provides a Prototype board and a Base board that makes it possible to make experiments and prototyping with many peripherals.

LPCXpresso Kit

The LPCXpresso Kit (EA-XPR-109) is a bundle containing the LPC1115 LPCXpresso Board (EA-XPR-009) and the LPCXpresso Base Board (EA-XPR-021).

SPECIFICATION

LPC1115 LPCXpresso Board

Processor NXP's Cortex-M0 LPC1115 microcontroller in LQFP48 package

Flash 64 kB

Data Memory 8 kB

Clock Crystals 12.000 MHz crystal for CPU

Dimensions 35 x 140 mm

Power 3.15V-3.3V external powering, or

from USB via JTAG probe (LPC-LINK)

Connectors All LPC1115 pins available on expansion connector (2x27 pin rows, 100 mil pitch, 900 mil between rows)

Other

• Embedded JTAG (LPC-LINK) functionality via LPCXpresso toolchain

• LPC-LINK can be connected to external target processor after modifications to the LPCXpresso board

• LED on PIO0_7


...

LPCXpresso Prototype Board Order number: EA-XPR-020 12€

LPCXpresso Base Board Order number: EA-XPR-021 89€


CMSIS - Cortex Microcontroller Software Interface Standard reading notes

CMSIS - Cortex Microcontroller Software Interface Standard

http://www.arm.com/products/processors/cortex-m/cortex-microcontroller-software-interface-standard.php

The ARM Cortex™ Microcontroller Software Interface Standard (CMSIS) is a vendor-independent hardware abstraction layer for the Cortex-M processor series. The CMSIS enables consistent and simple software interfaces to the processor and the peripherals, simplifying software re-use, reducing the learning curve for new microcontroller developers and reducing the time to market for new devices.

Creation of software is a major cost factor in the embedded industry. By standardizing the software interfaces across all Cortex-M silicon vendor products, especially when creating new projects or migrating existing software to a new device, means significant cost reductions.

...

The CMSIS consists of the following components:

CMSIS-CORE: provides an interface to Cortex-M0, Cortex-M3, Cortex-M4, SC000, and SC300 processors and peripheral registers

CMSIS-DSP: DSP library with over 60 functions in fixed-point (fractional q7, q15, q31) and single precision floating-point (32-bit) implementation

CMSIS-RTOS API: standardized programming interface for real-time operating systems for thread control, resource, and time management

CMSIS-SVD: System View Description XML files that contain the programmer's view of a complete microcontroller system including peripherals

The standard is fully scalable to ensure that it is suitable for all Cortex-M processor series microcontrollers. That is everything from the smallest 8 KB device up to devices with sophisticated communication peripherals such as Ethernet or USB. (The memory requirement for the Core Peripheral Functions is less than 1 KB code, less than 10 Bytes RAM).

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*** CMSIS Configuration Wizard Beta Easily configure ARM CMSIS files without Keil Brought to you by: amrbekhit

http://sourceforge.net/projects/cmsisconfig/

Description

The CMSIS Configuration Wizard allows users to easily configure ARM source files without using the Keil uVision IDE. The wizard parses the source file and generates a GUI, allowing the various parameters to be edited.

CMSIS Confi


*** LPCXpresso boards

LPCXpresso boards are sold by NXP to provide a quick and easy way for engineers to evaluate their microcontroller chips.[77][78] The LPCXpresso boards are jointly developed by NXP, Code Red Technologies,[37] and Embedded Artists.[19]

Each LPCXpresso board has the following common features:

On-board LPC-LINK for programming and debugging via a MiniUSB connector.

Board can be cut into two separate boards: LPC-LINK board and target microcontroller board.

Power input from 5 V via the USB cable or 5 V external power. If boards are separated, then 3.3 V external power is required for the target microcontroller board.

Target microcontroller side:

User LED.

12 MHz crystal.

Prototype area.

Holes for JTAG/SWD debugger connection.

DIP footprint compatible with mbed boards.

The following LPCXpresso boards exist:

...

LPC1114 LPCXpresso, p/n OM11049

...

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uVision MDK Cortex M0 LPC11xx startup files


Description of the LPC11xx Example Software Package 2010, NXP Semiconductor

https://github.com/Mrjohns42/RSL/tree/master/lpc11xx.keil-examples-CMSIS-update_2/lpc11xx.keil-examples-CMSIS-update

The Description of the Example software

This example demonstrates the use of build-in peripherals on the NXP
LPC11xx family microcontrollers.

The Example software includes, common library, peripheral APIs, and test modules
for the APIs. The common library include startup file, standard definition and
header files, processor specific setup module, generic interrupt related APIs, 
timer routine. The peripheral directories include, ADC, GPIO, timer, SPI, I2C, 
Watchdog timer, UART, external interrupt, various USB class drivers ,etc.

Depending on the configuration of LPC11xx, it may include a CAN controller
or a USB Device controller, or none of them. The header file of register 
definition, LPC11xx.h, the clock configuration, and the NVIC APIs, includes 
both CAN and USB, but may not apply to the MCU you are using.
  
The development environment is Keil's, an ARM company now, uVision MDK 3.85 
or later, and ULINK2 ICE. The target boards is NXP Internal Eval board with 
LPC11xx MCU on it.

Please note that, the latest Keil MDK may or may not include the startup file, 
the header files, and Cortex related API files for NVIC and Systick driver. These 
files are also included in our common library. If the users wish not to use Keil 
MDK, the compiler needs to: 

  (1) set up the include path to COMMON/INC

  (2) change #include <lpc11xx.h> to "#include "lpc11xx.h" where is located
under COMMON/INC directory. 

  (3) Add "core_cm0.c" from COMMON/SRC into your own project.

The project is created for both target option "FLASH(Release)" and "RAM(Debug)". 
For "FLASH", the image code can be programmed into the flash and executed;
for "RAM", the image code can be loaded into internal SRAM(IRAM)
for easy debugging. The "RAM.ini" in each directory is a Keil uVision debugger
script file, once the debugger starts, the code will be loaded to the IRAM
first, then, "RAM.ini" will be executed and reset program counter(PC) to 
0x10000000(IRAM starting address) that code will be executed from.

For Flash Update, a FLM file for Keil MDK built-n flash utility is included if 
the revision of Keil MDK you have doesn't support LPC11xx yet. If the LPC11xx 
is not listed in the Keil MDK Device Database, choose "Cortex M0" as shown in 
our example project file, then, copy the file "LPC_IAP_CD0_32.FLM" from Sample Code
Bundle Root directory to "C:\Keil\ARM\Flash". Now, you go to "Options/Utilities/Flash 
Programming Setting", add "LPC114x IAP 32kB Flash" from a list of flash algorithm,
and use the Keil Built-in flash utility to program the flash.

Some external components, such as I2C temperature, SPI serial EEPROM, will be 
required to add on the board in order to complete the test below.

Known problems: 

    (1) Keil MDK configuration Wizard has not been tested for Clock configuration.

    (2) When using Flash download, at the end of the flash update, GUI shows
"Error: Flash download failed, Cortex M0". although, the flash has been updated
correctly. So, this message should be ignored. It depends on the revision of the
Keil MDK you use. For MDK with LPC11xx support, this shouldn't be an issue.


The directory tree and content of the sample software

common
    -- inc
-- lpc11xx.h CMSIS Cortex-M0 Core Peripheral Access Layer Header 
File for NXP LPC11xx Device Series 
-- core_cm0.h CMSIS Cortex-M0 Core Peripheral Access Layer Header File
-- system_LPC11xx.h CMSIS Cortex-M0 Device Peripheral Access Layer Header 
File for the NXP LPC11xx Device Series
-- type.h Type definition Header file for NXP LPC11xx Family
-- systick.h Cortex M0 Systemtick header and definition 
-- gpio.h GPIO setting and I/O pin connfigured as external interrupt
definition
-- uart.h UART setting header and definiton
-- timer16.h 16-bit TIMER setting header and definition
-- timer32.h 32-bit TIMER setting header and definition
-- clkconfig.h          clock configuration header and definition  
    -- src
-- core_cm0.c CMSIS Cortex-M0 Core Peripheral Access Layer Source File
-- startup_LPC11xx.s CMSIS Cortex-M0 Core Device Startup File 
            for the NXP LPC11xx Device Series
-- system_LPC11xx.c CMSIS Cortex-M0 Device Peripheral Access Layer Source
    File for the NXP LPC11xx Device Series
-- gpio.c GPIO setting APIs and I/O pin connfigured as external 
interrupt and interrupt handler
-- uart.c UART setting API and interrupt handler
-- timer16.c 16-bit TIMER setting APIs and interrupt handler
-- timer32.c 32-bit TIMER setting APIs and interrupt handler
-- clkconfig.c Misc. clock configuration setting and APIs in addition
to system_lpc11xx.c  

Blinky
    -- blinky.c General test, GPIO, Timer and NVIC test module, note: 
API modules are in the COMMON directory and 
shared and used by some other peripheral testing.
    -- blinky.uvproj uVision 4.x project file    

ADC
    -- adc.h ADC header
    -- adc.c ADC APIs
    -- adctest.c ADC controller test module
    -- adc.uvproj uVision 4.x project file


GPIO
    -- gpiotest.c External interrupt test module, APIs are 
from COMMON directory
    -- gpio.uvproj uVision 4.x project file

Systick
    -- systick.c ARM Cortext M0 Core system tick test module, APIs 
are from COMMON directory
    -- systick.uvproj uVision 4.x project file
                
I2C
    -- i2c.h I2C header
    -- i2c.c I2C APIs
    -- i2ctest.c I2C test module
    -- i2ctest.uvproj uVision 4.x project file

I2CSlave
    -- i2cslave.h I2C slave header
    -- i2cslave.c I2C slave APIs
    -- i2cslvtst.c I2C slave test module
    -- i2cslave.uvproj uVision 4.x project file

Timer32
    -- timer32test.c 32-bit Timer test module, note: API modules
are in the COMMON directory and 
shared and used by some other peripheral testing.
    -- timer32.uvproj uVision 4.x project file

PWM
    -- pwmtest.c PWM test module, note: PWM API modules
are in the COMMON directory, shared and used 
by some other peripheral testing.
    -- pwm.uvproj uVision 4.x project file

UART
    -- uarttest.c UART test module, note: UART API modules
are in the COMMON directory, shared and used 
by some other peripheral testing.
    -- uart.uvproj uVision 4.x project file

RS485
    -- rs485.h RS485 header
    -- rs485.c RS485 APIs
    -- rs485test.c RS485 test module
    -- rs485.uvproj uVision 4.x project file

WDT
    -- wdt.h Watchdog timer header
    -- wdt.c Watchdog timer APIs
    -- wdttest.c Watchdog timer test module
    -- wdt.uvproj uVision 4.x project file

CAN
    -- can.h CAN header
    -- can.c CAN APIs
    -- cantest.c CAN test module
    -- can.uvproj uVision 4.x project file

CAN on_chip
    -- rom_driver_CAN.h CAN on-chip API function header
    -- rom_drivers.h ROM drivers header
    -- main.c CAN on-chip test module
    -- CAN on_chip.uvproj uVision 4.x project file

CANopen on_chip
    -- rom_driver_CAN.h CAN on-chip API function header
    -- rom_drivers.h ROM drivers header
    -- main.c CAN on-chip test module
    -- CANopen on_chip.uvproj uVision 4.x project file

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References

* The Definitive Guide to the ARM Cortex-M0 By Joseph Yiu


* Startup and system files for LPC11xx Cortex M0  MDK 4.13 or higher:

Keil\ARM\Startup\NXP\LPC11xx\startup_LPC11xx.a

Keil\ARM\Startup\NXP\LPC11xx\system_LPC11xx.c

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Saturday, 6 July 2013

uv4 code size limit is only 32K!























When I tried the debug thing.  I found a big problem.


The evaluation mode code size limit is only 32K!


I guess 32K is very small, not that useful.  Perhaps I should consider forgetting uv4 and start looking for other free tools more generous than uv4.

How disappointing!

I call it a day.

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